The Effect of Wire Length Minimization on Yield
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چکیده
Wire length minimization ( W L M ) has received szgnificant attention in the compaction stage of VLSI layout synthesis. In most cases, reduction in wire length also results in better circuit yield. However, a trade-off may stall exist between total wire length and yield. In WLM only the area/length of the layout patterns is considered whereas for yield enhancement both the area of the layout patterns and the spacing among them must be considered. The trade-off between these two features is analyzed on a set of benchmark layouts in this paper.
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تاریخ انتشار 1994